Neuropixels V1

Authors:

Jonathan P. Newman

Version:

1

IO:

Frame Source, Register Access

ONIX ID:

11

ONIX Hubs:

Neuropixels-1.0 Headstage

Description

The Neuropixels V1 Device acquires data from Neuropixels V1 probes.

Register Programming

Managed Registers

Managed register access is provided at offset 0x8000.

Managed Registers

Address	Name	Access	Time of Effect	POR Value	Reset Action	Description
0x8000	ENABLE	R/W	On Reset	Implementation dependent, see hub documentation	None	The LSB is used to enable or disable the device data stream: 0x0: data output disabled 0x1: data output enabled

Unmanaged Registers

Direct, unmanaged read and write access is provided to the Neuropixels V1 registers, which are reproduced here for clarity. The time of effect of changes to these registers are defined by the probe. Complete documentation is available through IMEC.

Unmanaged Registers

Address	Name	Access	Time of Effect	POR Value	Reset Action	Description
0x00	OP_MODE	R/W	See IMEC docs	“00000000”	None	Operation mode register.
0x01	REC_MOD	R/W	See IMEC docs	“11000000”	None	Recording flags register.
0x02	CAL_MOD	R/W	See IMEC docs	“00000000”	None	Calibration flags register.
0x03	TEST_CONFIG1	R/W	See IMEC docs	“00000000”	None	Test configuration register 1.
0x04	TEST_CONFIG2	R/W	See IMEC docs	“00000000”	None	Test configuration register 2.
0x05	TEST_CONFIG3	R/W	See IMEC docs	“00000000”	None	Test configuration register 3.
0x06	TEST_CONFIG4	R/W	See IMEC docs	“00000000”	None	Test configuration register 4.
0x07	TEST_CONFIG5	R/W	See IMEC docs	“00000000”	None	Test configuration register 5.
0x08	STATUS	R/W	See IMEC docs	“00000000”	None	Shift register error status.
0x09	SYNC	R/W	See IMEC docs	“00000000”	None	Sync code for delineating data frames.
0x0a	SR_CHAIN5	R/W	See IMEC docs	“00000000”	None	Shift register chain 5.
0x0b	SR_CHAIN4	R/W	See IMEC docs	“00000000”	None	Shift register chain 4.
0x0c	SR_CHAIN3	R/W	See IMEC docs	“00000000”	None	Shift register chain 3.
0x0d	SR_CHAIN2	R/W	See IMEC docs	“00000000”	None	Shift register chain 2.
0x0e	SR_CHAIN1	R/W	See IMEC docs	“00000000”	None	Shift register chain 1.
0x0f	SR_LENGTH2	R/W	See IMEC docs	“00000000”	None	Shift register byte read length 2.
0x10	SR_LENGTH1	R/W	See IMEC docs	“00000000”	None	Shift register byte read length 1.
0x11	SOFT_RESET	R/W	See IMEC docs	“00000000”	None	Software issued synchronous reset.

Device To Host Data Frames

Each frame transmitted to the host consists of a single Neuropixels V1 “Super Frame” containing all 384 AP channels and a single set of 32 LFP channels. Twelve of Super Frames are required to construct a single “Ultra Frame” which contains 12 samples from each the 384 AP channels and a single sample from each of the 384 LFP channels.

Each ONIX frame is organized as follows:

Here, LFP and AP “Frames” are not actually 32-bits words but full, 32-ADC sample blocks. Each one of these blocks is organized as follows:

Definitions for each of these fields are as follows:

Sync Type

Fixed word indicating the frame type - 207: Normal frame. Frame contains AP data. - 816: Super frame start. Frame contains LFP data.

ADC Voltage

Unsigned integer. Only the 10 LSBs are valid.

Frame Counter

A looping 24-bit frame counter produced by the probe to detect dropped frames and to ensure proper reset sequence that results in a count of 0 at the start of transmission.

Host To Device Data Frames

This device does not accept input frames. All write attempts will fail with an error.